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yosys: Open Synthesis suite1
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
... part of T2, get it here
URL: https://yosyshq.net/yosys/
Author: Claire Xenia Wolf <claire [at] clairexen [dot] net>
Maintainer: Rene Rebe <rene [at] t2-project [dot] org>
License: ISC
Status: Beta
Version: 0.51
Download: https://github.com/YosysHQ/yosys/tags/download/v0.51/ yosys.tar.gz
T2 source: yosys.cache
T2 source: yosys.desc
T2 source: yosys.prof
Build time (on reference hardware): 760% (relative to binutils)2
Installed size (on reference hardware): 47.64 MB, 329 files
Dependencies (build time detected): bash binutils bison coreutils diffutils flex gawk gettext grep gzip libffi linux-header m4 make pkgconfig python readline sed tar tbb tcl zlib
Installed files (on reference hardware):
[show]
usr/bin/yosys
usr/bin/yosys-abc
usr/bin/yosys-config
usr/bin/yosys-filterlib
usr/bin/yosys-smtbmc
usr/bin/yosys-witness
usr/share/yosys
usr/share/yosys/abc9_map.v
usr/share/yosys/abc9_model.v
usr/share/yosys/abc9_unmap.v
usr/share/yosys/achronix/speedster22i/cells_map.v
usr/share/yosys/achronix/speedster22i/cells_sim.v
usr/share/yosys/adff2dff.v
usr/share/yosys/anlogic/arith_map.v
usr/share/yosys/anlogic/brams.txt
usr/share/yosys/anlogic/brams_map.v
usr/share/yosys/anlogic/cells_map.v
usr/share/yosys/anlogic/cells_sim.v
usr/share/yosys/anlogic/eagle_bb.v
usr/share/yosys/anlogic/lutrams.txt
usr/share/yosys/anlogic/lutrams_map.v
usr/share/yosys/cells.lib
usr/share/yosys/cmp2lcu.v
usr/share/yosys/cmp2lut.v
usr/share/yosys/cmp2softlogic.v
usr/share/yosys/coolrunner2/cells_counter_map.v
usr/share/yosys/coolrunner2/cells_latch.v
usr/share/yosys/coolrunner2/cells_sim.v
usr/share/yosys/coolrunner2/tff_extract.v
usr/share/yosys/coolrunner2/xc2_dff.lib
usr/share/yosys/dff2ff.v
usr/share/yosys/ecp5/arith_map.v
usr/share/yosys/ecp5/brams.txt
usr/share/yosys/ecp5/brams_map.v
usr/share/yosys/ecp5/cells_bb.v
usr/share/yosys/ecp5/cells_ff.vh
usr/share/yosys/ecp5/cells_io.vh
usr/share/yosys/ecp5/cells_map.v
usr/share/yosys/ecp5/cells_sim.v
usr/share/yosys/ecp5/dsp_map.v
usr/share/yosys/ecp5/latches_map.v
usr/share/yosys/ecp5/lutrams.txt
usr/share/yosys/ecp5/lutrams_map.v
usr/share/yosys/efinix/arith_map.v
usr/share/yosys/efinix/brams.txt
usr/share/yosys/efinix/brams_map.v
usr/share/yosys/efinix/cells_map.v
usr/share/yosys/efinix/cells_sim.v
usr/share/yosys/efinix/gbuf_map.v
usr/share/yosys/fabulous/arith_map.v
usr/share/yosys/fabulous/cells_map.v
usr/share/yosys/fabulous/ff_map.v
usr/share/yosys/fabulous/io_map.v
usr/share/yosys/fabulous/latches_map.v
usr/share/yosys/fabulous/prims.v
usr/share/yosys/fabulous/ram_regfile.txt
usr/share/yosys/fabulous/regfile_map.v
usr/share/yosys/gate2lut.v
usr/share/yosys/gatemate/arith_map.v
usr/share/yosys/gatemate/brams.txt
usr/share/yosys/gatemate/brams_init_20.vh
usr/share/yosys/gatemate/brams_init_40.vh
usr/share/yosys/gatemate/brams_map.v
usr/share/yosys/gatemate/cells_bb.v
usr/share/yosys/gatemate/cells_sim.v
usr/share/yosys/gatemate/inv_map.v
usr/share/yosys/gatemate/lut_map.v
usr/share/yosys/gatemate/lut_tree_cells.genlib
usr/share/yosys/gatemate/lut_tree_map.v
usr/share/yosys/gatemate/mul_map.v
usr/share/yosys/gatemate/mux_map.v
usr/share/yosys/gatemate/reg_map.v
usr/share/yosys/gowin/arith_map.v
usr/share/yosys/gowin/brams.txt
usr/share/yosys/gowin/brams_map.v
usr/share/yosys/gowin/cells_map.v
usr/share/yosys/gowin/cells_sim.v
usr/share/yosys/gowin/cells_xtra.v
usr/share/yosys/gowin/lutrams.txt
usr/share/yosys/gowin/lutrams_map.v
usr/share/yosys/greenpak4/cells_blackbox.v
usr/share/yosys/greenpak4/cells_latch.v
usr/share/yosys/greenpak4/cells_map.v
usr/share/yosys/greenpak4/cells_sim.v
usr/share/yosys/greenpak4/cells_sim_ams.v
usr/share/yosys/greenpak4/cells_sim_digital.v
usr/share/yosys/greenpak4/cells_sim_wip.v
usr/share/yosys/greenpak4/gp_dff.lib
usr/share/yosys/ice40/abc9_model.v
usr/share/yosys/ice40/arith_map.v
usr/share/yosys/ice40/brams.txt
usr/share/yosys/ice40/brams_map.v
usr/share/yosys/ice40/cells_map.v
usr/share/yosys/ice40/cells_sim.v
usr/share/yosys/ice40/dsp_map.v
usr/share/yosys/ice40/ff_map.v
usr/share/yosys/ice40/latches_map.v
usr/share/yosys/ice40/spram.txt
usr/share/yosys/ice40/spram_map.v
usr/share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
usr/share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
usr/share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
usr/share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
usr/share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
usr/share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
usr/share/yosys/include/backends/rtlil/rtlil_backend.h
usr/share/yosys/include/frontends/ast/ast.h
usr/share/yosys/include/frontends/ast/ast_binding.h
usr/share/yosys/include/frontends/blif/blifparse.h
usr/share/yosys/include/kernel/binding.h
usr/share/yosys/include/kernel/cellaigs.h
usr/share/yosys/include/kernel/celledges.h
usr/share/yosys/include/kernel/celltypes.h
usr/share/yosys/include/kernel/consteval.h
usr/share/yosys/include/kernel/constids.inc
usr/share/yosys/include/kernel/cost.h
usr/share/yosys/include/kernel/ff.h
usr/share/yosys/include/kernel/ffinit.h
usr/share/yosys/include/kernel/ffmerge.h
usr/share/yosys/include/kernel/fmt.h
usr/share/yosys/include/kernel/fstdata.h
usr/share/yosys/include/kernel/hashlib.h
usr/share/yosys/include/kernel/json.h
usr/share/yosys/include/kernel/log.h
usr/share/yosys/include/kernel/macc.h
usr/share/yosys/include/kernel/mem.h
usr/share/yosys/include/kernel/modtools.h
usr/share/yosys/include/kernel/qcsat.h
usr/share/yosys/include/kernel/register.h
usr/share/yosys/include/kernel/rtlil.h
usr/share/yosys/include/kernel/satgen.h
usr/share/yosys/include/kernel/sigtools.h
usr/share/yosys/include/kernel/timinginfo.h
usr/share/yosys/include/kernel/utils.h
usr/share/yosys/include/kernel/yosys.h
usr/share/yosys/include/kernel/yw.h
usr/share/yosys/include/libs/ezsat/ezminisat.h
usr/share/yosys/include/libs/ezsat/ezsat.h
usr/share/yosys/include/libs/fst/fstapi.h
usr/share/yosys/include/libs/json11/json11.hpp
usr/share/yosys/include/libs/sha1/sha1.h
usr/share/yosys/include/passes/fsm/fsmdata.h
usr/share/yosys/intel/common/altpll_bb.v
usr/share/yosys/intel/common/brams_m9k.txt
usr/share/yosys/intel/common/brams_map_m9k.v
usr/share/yosys/intel/common/ff_map.v
usr/share/yosys/intel/common/m9k_bb.v
usr/share/yosys/intel/cyclone10lp/cells_map.v
usr/share/yosys/intel/cyclone10lp/cells_sim.v
usr/share/yosys/intel/cycloneiv/cells_map.v
usr/share/yosys/intel/cycloneiv/cells_sim.v
usr/share/yosys/intel/cycloneive/cells_map.v
usr/share/yosys/intel/cycloneive/cells_sim.v
usr/share/yosys/intel/max10/cells_map.v
usr/share/yosys/intel/max10/cells_sim.v
usr/share/yosys/intel_alm/common/abc9_map.v
usr/share/yosys/intel_alm/common/abc9_model.v
usr/share/yosys/intel_alm/common/abc9_unmap.v
usr/share/yosys/intel_alm/common/alm_map.v
usr/share/yosys/intel_alm/common/alm_sim.v
usr/share/yosys/intel_alm/common/arith_alm_map.v
usr/share/yosys/intel_alm/common/bram_m10k.txt
usr/share/yosys/intel_alm/common/bram_m10k_map.v
usr/share/yosys/intel_alm/common/bram_m20k.txt
usr/share/yosys/intel_alm/common/bram_m20k_map.v
usr/share/yosys/intel_alm/common/dff_map.v
usr/share/yosys/intel_alm/common/dff_sim.v
usr/share/yosys/intel_alm/common/dsp_map.v
usr/share/yosys/intel_alm/common/dsp_sim.v
usr/share/yosys/intel_alm/common/lutram_mlab.txt
usr/share/yosys/intel_alm/common/megafunction_bb.v
usr/share/yosys/intel_alm/common/mem_sim.v
usr/share/yosys/intel_alm/common/misc_sim.v
usr/share/yosys/intel_alm/common/quartus_rename.v
usr/share/yosys/intel_alm/cyclonev/cells_sim.v
usr/share/yosys/lattice/arith_map_ccu2c.v
usr/share/yosys/lattice/arith_map_ccu2d.v
usr/share/yosys/lattice/brams_16kd.txt
usr/share/yosys/lattice/brams_8kc.txt
usr/share/yosys/lattice/brams_map_16kd.v
usr/share/yosys/lattice/brams_map_8kc.v
usr/share/yosys/lattice/ccu2c_sim.vh
usr/share/yosys/lattice/ccu2d_sim.vh
usr/share/yosys/lattice/cells_bb_ecp5.v
usr/share/yosys/lattice/cells_bb_xo2.v
usr/share/yosys/lattice/cells_bb_xo3.v
usr/share/yosys/lattice/cells_bb_xo3d.v
usr/share/yosys/lattice/cells_ff.vh
usr/share/yosys/lattice/cells_io.vh
usr/share/yosys/lattice/cells_map.v
usr/share/yosys/lattice/cells_sim_ecp5.v
usr/share/yosys/lattice/cells_sim_xo2.v
usr/share/yosys/lattice/cells_sim_xo3.v
usr/share/yosys/lattice/cells_sim_xo3d.v
usr/share/yosys/lattice/common_sim.vh
usr/share/yosys/lattice/dsp_map_18x18.v
usr/share/yosys/lattice/latches_map.v
usr/share/yosys/lattice/lutrams.txt
usr/share/yosys/lattice/lutrams_map.v
usr/share/yosys/mul2dsp.v
usr/share/yosys/nexus/arith_map.v
usr/share/yosys/nexus/brams.txt
usr/share/yosys/nexus/brams_map.v
usr/share/yosys/nexus/cells_map.v
usr/share/yosys/nexus/cells_sim.v
usr/share/yosys/nexus/cells_xtra.v
usr/share/yosys/nexus/dsp_map.v
usr/share/yosys/nexus/latches_map.v
usr/share/yosys/nexus/lrams.txt
usr/share/yosys/nexus/lrams_map.v
usr/share/yosys/nexus/lutrams.txt
usr/share/yosys/nexus/lutrams_map.v
usr/share/yosys/nexus/parse_init.vh
usr/share/yosys/pmux2mux.v
usr/share/yosys/python3/smtio.py
usr/share/yosys/python3/ywio.py
usr/share/yosys/quicklogic/common/cells_sim.v
usr/share/yosys/quicklogic/pp3/abc9_map.v
usr/share/yosys/quicklogic/pp3/abc9_model.v
usr/share/yosys/quicklogic/pp3/abc9_unmap.v
usr/share/yosys/quicklogic/pp3/cells_map.v
usr/share/yosys/quicklogic/pp3/cells_sim.v
usr/share/yosys/quicklogic/pp3/ffs_map.v
usr/share/yosys/quicklogic/pp3/latches_map.v
usr/share/yosys/quicklogic/pp3/lut_map.v
usr/share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
usr/share/yosys/quicklogic/qlf_k6n10f/arith_map.v
usr/share/yosys/quicklogic/qlf_k6n10f/bram_types_sim.v
usr/share/yosys/quicklogic/qlf_k6n10f/brams_map.v
usr/share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
usr/share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
usr/share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
usr/share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
usr/share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
usr/share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
usr/share/yosys/quicklogic/qlf_k6n10f/libmap_brams.txt
usr/share/yosys/quicklogic/qlf_k6n10f/libmap_brams_map.v
usr/share/yosys/quicklogic/qlf_k6n10f/sram1024x18_mem.v
usr/share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v
usr/share/yosys/sf2/arith_map.v
usr/share/yosys/sf2/cells_map.v
usr/share/yosys/sf2/cells_sim.v
usr/share/yosys/simcells.v
usr/share/yosys/simlib.v
usr/share/yosys/smtmap.v
usr/share/yosys/techmap.v
usr/share/yosys/xilinx/abc9_model.v
usr/share/yosys/xilinx/arith_map.v
usr/share/yosys/xilinx/brams_defs.vh
usr/share/yosys/xilinx/brams_xc2v.txt
usr/share/yosys/xilinx/brams_xc2v_map.v
usr/share/yosys/xilinx/brams_xc3sda.txt
usr/share/yosys/xilinx/brams_xc3sda_map.v
usr/share/yosys/xilinx/brams_xc4v.txt
usr/share/yosys/xilinx/brams_xc4v_map.v
usr/share/yosys/xilinx/brams_xc5v_map.v
usr/share/yosys/xilinx/brams_xc6v_map.v
usr/share/yosys/xilinx/brams_xcu_map.v
usr/share/yosys/xilinx/brams_xcv.txt
usr/share/yosys/xilinx/brams_xcv_map.v
usr/share/yosys/xilinx/cells_map.v
usr/share/yosys/xilinx/cells_sim.v
usr/share/yosys/xilinx/cells_xtra.v
usr/share/yosys/xilinx/ff_map.v
usr/share/yosys/xilinx/lut_map.v
usr/share/yosys/xilinx/lutrams_xc5v.txt
usr/share/yosys/xilinx/lutrams_xc5v_map.v
usr/share/yosys/xilinx/lutrams_xcu.txt
usr/share/yosys/xilinx/lutrams_xcv.txt
usr/share/yosys/xilinx/lutrams_xcv_map.v
usr/share/yosys/xilinx/mux_map.v
usr/share/yosys/xilinx/urams.txt
usr/share/yosys/xilinx/urams_map.v
usr/share/yosys/xilinx/xc3s_mult_map.v
usr/share/yosys/xilinx/xc3sda_dsp_map.v
usr/share/yosys/xilinx/xc4v_dsp_map.v
usr/share/yosys/xilinx/xc5v_dsp_map.v
usr/share/yosys/xilinx/xc6s_dsp_map.v
usr/share/yosys/xilinx/xc7_dsp_map.v
usr/share/yosys/xilinx/xcu_dsp_map.v
var/adm/dependencies/yosys
var/adm/descs/yosys
var/adm/flists/yosys
var/adm/md5sums/yosys
var/adm/packages/yosys
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2) Compatible with Linux From Scratch's "Standard Build Unit" (SBU).
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