T2 package - trunk - iverilog - A Verilog simulation and synthesis tool

iverilog: A Verilog simulation and synthesis tool¹

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format.

... part of T2, get it here

URL: http://iverilog.icarus.com/

Author: David Evans yevans@virginia.edu>
Maintainer: T2 Project <t2 [at] t2-project [dot] org>

License: GPL
Status: Beta
Version: 11.0

Remark: Does cross compile (as setup and patched in T2).

Download: http://dl.sourceforge.net/iverilog/ verilog-11.0.tar.gz

T2 source: iverilog.cache
T2 source: iverilog.desc

Build time (on reference hardware): 90% (relative to binutils)²

Installed size (on reference hardware): 5.85 MB, 59 files

Dependencies (build time detected): 00-dirtree bash binutils bison bzip2 coreutils diffutils findutils flex gawk grep gzip linux-header m4 make readline sed tar zlib

Installed files (on reference hardware): [show]

¹) This page was automatically generated from the T2 package source. Corrections, such as dead links, URL changes or typos need to be performed directly on that source.

²) Compatible with Linux From Scratch's "Standard Build Unit" (SBU).

iverilog: A Verilog simulation and synthesis tool1

iverilog: A Verilog simulation and synthesis tool¹