Package available in: [trunk]
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
Author: Clifford Wolf <clifford [at] clifford [dot] at>
Maintainer: Rene Rebe <rene [at] t2-project [dot] org>
Build time (on reference hardware): n.a.
Installed size (on reference hardware): n.a.
Dependencies (build time detected): n.a.
Installed files (on reference hardware): n.a.
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