yosys: Open Synthesis suite1
Package available in: [trunk]
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
... part of T2, get it here
URL: http://www.clairexen.net/yosys/
Author: Claire Xenia Wolf <claire [at] clairexen [dot] net>
Maintainer: Rene Rebe <rene [at] t2-project [dot] org>
License: ISC
Status: Beta
Version: 0.27
Download: https://github.com/YosysHQ/yosys/ releases
Download: https://github.com/YosysHQ/abc/ releases
T2 source: abc-cc.patch
T2 source: yosys.cache
T2 source: yosys.conf
T2 source: yosys.desc
T2 source: yosys.prof
Build time (on reference hardware): 330% (relative to binutils)2
Installed size (on reference hardware): 22.23 MB, 244 files
Dependencies (build time detected): 00-dirtree binutils bison coreutils diffutils findutils flex gawk grep libffi m4 make ncurses patch python readline sed tar tcl zlib
Installed files (on reference hardware): n.a.
1) This page was automatically generated from the T2 package source. Corrections, such as dead links, URL changes or typos need to be performed directly on that source.
2) Compatible with Linux From Scratch's "Standard Build Unit" (SBU).