Package available in: [trunk]
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
Author: The Project Trellis Authors
Maintainer: Rene Rebe <rene [at] t2-project [dot] org>
Build time (on reference hardware): 10% (relative to binutils)2
Installed size (on reference hardware): 63.45 MB, 435 files
Dependencies (build time detected): 00-dirtree bash binutils boost cmake coreutils diffutils findutils gawk gcc glibc grep linux-header make ncurses openssl patch python readline sed sysfiles tar zlib zstd
Installed files (on reference hardware): n.a.
1) This page was automatically generated from the T2 package source. Corrections, such as dead links, URL changes or typos need to be performed directly on that source.
2) Compatible with Linux From Scratch's "Standard Build Unit" (SBU).