iverilog: A Verilog simulation and synthesis tool1
Package available in: [trunk] [8.0] [7.0]
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format.
... part of T2, get it here
URL: http://iverilog.icarus.com/
Author: David Evans yevans@virginia.edu>
Maintainer: T2 Project <t2 [at] t2-project [dot] org>
License: GPL
Status: Beta
Version: 11.0
Remark: Does cross compile (as setup and patched in T2).
Download: http://dl.sourceforge.net/iverilog/ verilog-11.0.tar.gz
T2 source: iverilog.cache
T2 source: iverilog.desc
Build time (on reference hardware): 40% (relative to binutils)2
Installed size (on reference hardware): 5.85 MB, 59 files
Dependencies (build time detected): 00-dirtree binutils bison bzip2 coreutils diffutils findutils flex gawk grep linux-header m4 make ncurses readline sed tar zlib
Installed files (on reference hardware):
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1) This page was automatically generated from the T2 package source. Corrections, such as dead links, URL changes or typos need to be performed directly on that source.
2) Compatible with Linux From Scratch's "Standard Build Unit" (SBU).